(1) Field of the Invention
The present invention relates generally to semiconductors, and in particular, to a method of improving substantially the contact resistance of interconnect vias by means of stepwise deposition of metal at relatively low temperatures.
(2) Description of the Related Art
The performance of semiconductor integrated circuits is governed to a large extent by the electrical characteristics of its components. The components consist of electronic devices themselves where transistor action takes place, and the circuitry that connects the various components together. In the metal-oxide-semiconductors (MOS), the devices include the gate-source-drain, while in bipolars, the base-emitter-collector. The rest of the circuitry, namely, the micro-wires or the lines that connect the devices through various layers of the semiconductor are, for the most part, similar functionally and physically in both the MOS and bipolar technologies. Furthermore, the unit electrical resistance of the metal lines, or interconnects, are usually insignificant in comparison with the electrical resistance that is encountered at places where the lines make physical connection with each other or with the devices mentioned above. If the connection is to be made between components at different elevations, or levels, that are electrically insulated from each other within a semiconductor, then holes are formed in the insulators so that connections can be made through metal deposited into holes between the levels. Holes that reach over the devices that are normally at the lowest level are referred to as the "contact" holes. If, on the other hand, the holes are between the upper levels of the circuitry, those holes are referred to as the "via" holes. The metal that fills these holes are called the "contact-plug," and the "via-plug", respectively. It is the contact resistance that is offered to current flow at the interfaces between the "plugs" and the mating metal surfaces that governs, to a large extent, the performance of semiconductor integrated circuits.
The interconnections so formed through the "contact-plugs" or the "via-plugs" exhibit resistance (or impedance in the general case) to the flow of electric current through them. The nature of this electrical behavior can significantly impact the circuit performance of integrated circuits. Usually, the electrical resistance of the solid metal plugs themselves is small in comparison with the interfacial resistance that exists between the plugs and the contact surface that they are deposited on. When the contact surface is the silicon (Si) substrate, the interfacial or the contact resistance, R.sub.cs, becomes a part of a parasitic resistance, R.sub.p, that exists in the path between the metal plug-to-Si substrate interface and the region in the device where the actual transistor action begins. The various other resistances within the devices themselves that contribute to the total R.sub.p are well known and as they are not significant to the invention, will not be described in detail here. It is also known that the contribution of the contact resistance R.sub.cs of the metal-Si interface can be significant and that many methods have been devised to reduce its contribution to the over-all resistance, R.sub.p. It is of interest to note that a similar contact resistance, R.sub.cm, but at a metal-to-metal interface, exists with the "via-plugs" that connect the upper level metals in the upper interconnect layers. While many methods are available for improving the integrity of the metal-Si contact interface, as noted above, few exist for metal-metal interfaces in the via-plugs, which is the main concern of the present invention.
It will be appreciated in general that the via-plugs that connect one layer of metal lines with another at another level in a semiconductor substrate must be of good quality. That is, the metal must have good physical properties, it must fill the hole well, and most importantly, must form a good interfacial contact with the metal lines that it is connecting together. Because of its properties, aluminum (Al) is well suited for fabrication of metal interconnect lines. However, one major limitation has been the formation of hillocks at relatively low processing temperatures above 300.degree. C. As is well known in the art, hillocks are spike-like projections that erupt in response to a state of compressive stress in metal films and consequently protrude from the film's surface. When the protrusions penetrate the dielectric layer that separates the neighboring metal lines, they can cause interlevel shorting. Hillocks arise as a consequence of the low melting point of Al (660.degree. C.) which promotes high rate of vacancy diffusion in Al films. To inhibit vacancy diffusion through the grain boundaries, elements are usually added in excess of the solid solubility limit in the aluminum, thereby causing the elements to precipitate out and "plug" the grain boundaries. Both copper (Cu) and silicon (Si) are used for this purpose to form Al:Si:Cu, or Al:Cu films, but copper has been found to be more effective in this application.
It has also been found in the practice of the present invention that Al:Cu films perform substantially better than Al:Si:Cu films in relation to contact resistance in the via holes. It is because, a second factor is involved in the formation of surface protuberances such as hillocks at interfaces between metal and silicon, or even between contacting metal surfaces themselves. When the thermal coefficient of expansion of two neighboring materials are significantly different, such as that of Al (23.5.times.10.sup.-6 /.degree. C.) and Si (2.5.times.10.sup.-6 /.degree. C.), then, when the substrate is heated, a compressive stress develops which in turn causes nodules of metal to dislodge from the film and form an irregular interface. This is illustrated in FIG. 1a where a rough interface (20) is depicted at the bottom of the via plug (22). In the underlying process of FIG. 1a, an insulating layer (12), such as a reflow glass or other oxide layer as known in the art, is formed over a metal-1 layer (10), such as Al:Si:Cu, on a substrate. A via hole is opened through the oxide layer (12) using a mask and a conventional isotropic etching technique until metal-1 is reached. Then, a barrier metal (14), such as a refractory metal, metal nitride, metal silicide, or combination thereof, is deposited over the surface of the substrate. Layer (14) is deposited conformally to cover the bottom and sidewalls of the via hole. When metal-2 (16) is deposited subsequently, especially Al:Si:Cu, without stepwise staging, and/or at unfavorable substrate temperatures as described below, then poor interface (20) is formed between the via-plug (22) and the underlying metal layer (10), thus giving rise to poor contact resistance.
The problems cited above are exacerbated by the advent of the submicron semiconductor technology because of the smaller geometries. The smaller via holes tend to have a larger aspect ratio (height to width ratio) thereby making it more difficult to fill the holes with the attendant magnification of the poor contact resistance problem. It will be appreciated that the contact resistance is a function of the area at the bottom of the via hole. Sloped sidewalls that were used to improve metal flow into the vias with larger geometry devices are now becoming a liability as device sizes shrink because they consume too much area on a semiconductor chip. Consequently, attention is turning more and more to the metallurgical as well electrical properties of the metal itself. For example, refractory metal is being used in the vias in conjunction with the aluminum interconnect layer to improve the electrical conduction through the via. Some other metals used include titanium (Ti), titanium-tungsten (Ti:W), chemical vapor deposited tungsten (CVD W), and polycrystalline silicon (polySi), thus forming the structures Al--Ti--Si, Al--Ti:W--Si, Al--CVD W--Si and Al--polySi--Si, respectively. Even more complex multilayered structures are used as discussed in S. Wolf, "Silicon Processing for the VLSI Era," vol.2, Lattice Press, Sunset Beach, Calif., 1990, pp. 131-133. where platinum-silicide (PtSi) and titanium-nitride (TiN), for example, are sandwiched to form Al--Ti:W--PtSi--Si and Al--TiN--Ti--Si contact metallurgies. The methods by which these structures are processed (e.g., sputtering, evaporating, etc.,) are well known in the art and as they are not significant to the invention, will not be described in detail here.
Still, aluminum and aluminum alloys are the most common interconnect metals that are used in silicon substrates today. Of the problems associated with depositing aluminum in via holes, there is also the formation of voids which in turn can cause high via resistance. U.S. Pat. No. 5,108,951 addresses the problem from the point of view of the temperature at which aluminum is deposited into the vias. It is claimed in said Patent that voids form in the vias because aluminum is deposited at a temperature which tends to encourage fairly large grain sizes. Therefore, it is proposed in the same Patent that the aluminum be deposited by heating the substrate to a temperature between about 380.degree. C. to 500.degree. C. where the lower the deposition temperature, the smaller is the grain size. In another U.S. Pat. No. 5,407,863, the temperature range from the initial stage of aluminum deposition to the final stage is in between about 180.degree. C. to 460.degree. C. However, the metal film is formed while the temperature is changed at least twice during deposition. In this manner, the grain sizes of each layer of metal film formed at a temperature level is different from the grain sizes formed at the next temperature level. Consequently, layers of metal film having different crystal grain sizes are laminated stepwise in such a way that the grain boundaries are not likely to align themselves in the direction of the film thickness to form a void. Here, the thickness of the respective films is controlled by controlling the amount of aluminum or aluminum alloy that is deposited, which in turn is controlled by the speed at which the deposition is accomplished. Since metal film is formed by the well-known sputtering process, it is possible to change the film forming speed by changing the speed or density of ions generated in argon (Ar) gas and collided against an aluminum (Al) target.
It will be noted that the techniques that are proposed in U.S. Pat. Nos. 5,108,951 and 5,407,863 are directed towards solving the problems of void formation in via holes and electromigration or stress migration in Al or Al alloy films, respectively. It will also be known to those in the art that there are competing mechanisms between lowering the metal deposition temperature so as to reduce the grain size on the one hand, and increasing the temperature to aid the flow of melt into the holes on the other. Also the speed of deposition enters into the picture, because proper adjustments must be made as a function of temperature so as to allow sufficient time for the melt to form at that temperature and flow without bridging, for example, at the mouth of the via hole. It is proposed in the present invention, a method whereby the variables involving temperatures, materials and deposition rates are formulated in such a way that the electrical integrity of the via-plugs in the via holes is further improved over prior art.
A still further requirement beyond attaining a physically and electrically sound (no voids, low bulk resistance) via-plug is good interfacial contact (contact resistance) between the plug and the metal interconnect lines. The integrity and characteristics of a metal-to-metal contact is determined by the processes and the materials used in forming the contact. One of the important steps in the basic process of forming contact is the preparation of the surface (metal-1 in (step 50) of FIG. 1b) prior to the deposition of metal-2 (step 56) into the via hole. For this purpose, a pre-sputter etch cleaning is used to remove native oxide layers in the via hole. This is shown as (step 52) of prior art FIG. 1b. In order to provide a good metallurgical as well as mechanically locking interface between the via-plug and the next level metal, titanium (Ti) is deposited conformally into the via hole, which is (step 54) It is further proposed in this invention that the second metal be deposited at least two different temperatures in order to improve the electrical resistance of the total via-plug including the contact resistance described before.